• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:

    公开号:NL1029337A1
    申请号:NL1029337
    申请日:2005-06-24
    公开日:2006-01-10
    发明作者:Ji-Hyun Kim
    申请人:Samsung Electronics Co Ltd；
    IPC主号:
    专利说明:

    Short indication: Self-adjusted differential amplifier
    The present invention relates generally to a differential amplifier, and more particularly to a self-set differential amplifier.
    A differential amplifier is a circuit that is commonly used to amplify an input signal. Such amplifiers enjoy widespread use in many applications, for example as an input buffer or a receiver. The differential amplifier is usually used as a signal channel receiving stage used for transmitting signals between integrated circuits or chips.
    The differential amplifier receives first and second input signals via two complementary input terminals for generating output signals on two complementary output terminals. In this way, the differential amplifiers can cover a large area. to achieve output voltage swing and high gain, and can be used to reduce common mode noise.
    Property 1 shows a diagram of a conventional differential amplifier.
    Referring to FIG. 1, the differential amplifier includes two input transistors M1 and M2 for receiving differential input signals, an active load comprising a current source, and a current source ISS for providing a constant current to the differential amplifier. The differential amplifier illustrated in FIG. 1 amplifies the differential input signals received through input terminals IN and INB and supplies amplified signals to output terminals OÜT and OUTB. In the following, a small signal gain of the differential amplifier of FIG. 1 will be described.
    A small signal amplification from an amplifier is generally expressed as a product of a small signal trans-duct. and a small signal output resistance from the amplifier. Thus, the gain of the differential amplifier measured on an output terminal OUT of the differential amplifier of FIG. 1 is expressed as in expression 1. In expression 1, gm2 represents a small signal transconductance of the input transistor M2, and r2 and r4 are respective small signal output resistors of the input transistor M2 and the transistor M4 which are connected to the output terminal OUT. <Expression 1>
    The gain Av in expression 1 represents the gain measured at the output terminal OUT of the differential amplifier illustrated in FIG. When the input signals are applied to the input terminals IN and INB, the voltage of the output terminal OUTB also changes. However, the voltage change at the output terminal OUTB is small since the transistor M3 connected to the output terminal OÜTB has a diode-connected configuration. Therefore, the differential amplifier illustrated in FIG. 1 has a gain Av as expressed in expression 1.
    The differential amplifier illustrated in Fig. 1 has a limited output swing through the current source and the active load and requires additional circuits for driving the current source to provide a constant current to the differential amplifier circuit. The differential amplifier illustrated in FIG. 1 thus consumes additional current through the additional circuits. The limitation of the output swings and. In addition, imbalance between the voltages at two output terminals OUT and OUTB reduce the noise margin in the circuit.
    A CMOS differential amplifier is described in the published Korean patent application no. 2000-0009114, entitled "DIFFERENTIAL AMPLIFIER". The CMOS differential amplifier obtains a high gain by receiving an input signal through a structure of a CMOS inverter, and requires no additional circuits for driving a current source or a voltage source. However, the CMOS differential amplifier described above is unable to provide a constant bias current.
    FIG. 2 shows a schematic of a conventional CMOS differential amplifier of the type described in the published Korean patent application no. 2000-0009114. . As shown in Fig. 2, the CMOS differential amplifier includes first and second differential gain sections 11 and 21, first and second high-voltage adjustment sections 12 and 22, and first and second low-voltage adjustment sections 13 and 23. The first and second differential gain sections 11 and 21 amplify differential input signals Vp and Vn through the CMOS inverters 14 and 15, and the CMOS inverters 24 and 25, respectively. The first and second high voltage bias sections 12 and 22 provide a high bias voltage according to the output of the first and second 1 differential gain sections 11 and 21. The first and second low voltage adjustment sections 13 and 23 provide a low bias voltage according to the output of the first and second differential gain sections 11 and 21.
    In the CMOS differential amplifier illustrated in FIG. 2, when the input voltage Vp increases with a low voltage level and the input voltage Vn decreases with a low voltage level (when complementary small signals are applied to the input terminals), the bias current in the first high voltage setting section 12 and the low current setting current 13 decreases, since the voltage of a node N10 decreases as a result of the increase in the voltage of the input signal Vp.
    Similarly, the bias current of the second high voltage bias section 22 decreases and the bias current in the second low voltage bias section 23 increases as the voltage of a node N20 increases due to the decrease of the voltage of the input signal Vn.
    On the other hand, when the input voltage Vp decreases with a small voltage level and the input voltage Vn with the small voltage level increases, the bias current in the first high voltage bias section 12 decreases and the bias current in the first low voltage bias section increases, since the voltage of a node N10 increases due to the decrease of the voltage of the input signal Vp.
    Similarly, the bias current in the second high voltage bias section 22 increases and the bias current in the second low voltage bias section 23 as the voltage of the node N20 decreases due to the increase in the voltage of the input signal Vn. The CMOS differential amplifier illustrated in FIG. 2 therefore has a misalignment of bias currents of the high voltage / low voltage bias sections and the first / second bias sections when the differential small signals are supplied thereto. This misadjustment of the bias currents has an undesirable effect on the gain, the range of the output sweep, and the frequency characteristics. of the differential amplifier, which leads to a decrease in amplifier performance.
    The present invention is therefore provided to remove one or more problems due to the limitations and disadvantages of the prior art described above.
    A feature of the present invention is to provide a differential amplifier that is capable of providing a substantially constant bias current without the need for additional circuits for driving. power sources or voltage sources.
    In one embodiment, the present invention is directed to a differential amplifier. The differential amplifier comprises a first current source that is connected between a first power voltage and a first node, and which is adapted to provide a first bias current in response to a control signal and an inverted control signal. A second current source is connected between a second power voltage and a second node and which is adapted to provide a second bias current in response to the control signal and the inverted control signal. ". A . the first inverter is connected between the first node and the second node and is adapted to amplify an input signal for generating an inverted output signal. A second inverter is connected between the first node and the second node and is arranged to amplify an inverted input signal for generating an output signal. A self-adjustment control circuit is connected between the first node and the second node and is arranged to generate the control signal and the inverted control signal for controlling the first bias current and the second bias current in response to the input signal and the inverted input signal.
    In one embodiment, the self-adjustment control circuit comprises: a third inverter adapted to amplify the input signal for generating the inverted control signal; and a fourth inverter adapted to amplify the inverted input signal to generate the control signal. The first, second, third and fourth inverters include CMOS inverters in which a first PMOS transistor and a first NMOS transistor are serially connected.
    In one embodiment, the first current source comprises: a first undercurrent source that is connected between the first power voltage and the first node and which is arranged. for "providing a first under bias current to the first node in response to the inverted control signal; and a second under current source that is connected between the first power voltage and the first node and which is arranged to provide a second under bias current to the first node in response to the control signal, wherein the second sub-bias current is complementarily controlled with respect to the first sub-bias current, and wherein the first current source adds the first sub-bias current and the second sub-bias current to generate the first bias current.
    In one embodiment, the second current source comprises: a first undercurrent drain which is connected between the second power voltage and the second node and which is arranged to provide a third under bias current to the second node in response to the inverted control signal; and a second undercurrent drain. which is connected between the second power voltage and the second node and which is adapted to provide a fourth bias current to the second node. response to the control signal, wherein the fourth sub-bias current is complementarily controlled with respect to the third sub-bias current, and wherein the second current source adds the third sub-bias current and the fourth sub-bias current to generate the second bias current.
    In one embodiment, the. first sub-bias current increases as the fourth sub-bias current increases, the first sub-bias current decreases as the fourth sub-bias current decreases, the second sub-bias current increases. increases when the third sub-bias current increases and the second sub-bias current decreases as the third sub-bias current decreases.
    In one embodiment, the magnitude of the first bias current is equal to that of the second bias current. The first undercurrent source and the second undercurrent source include second PMOS transistors, respectively, and the first undercurrent drain and the second undercurrent drain include second NMOS transistors, respectively. The second PMOS transistors and the second NMOS transistors operate in a linear region.
    In one embodiment, the first power voltage is approximately 1.8 volts and the second power voltage is approximately 0 volts. The input signal and the inverted input signal include small signals set to approximately 0.9 volts.
    According to the above exemplary embodiment of the present invention, a constant self-adjusted current is achieved without the need to use additional circuits for driving current sources or voltage sources. In addition, a large gain and a wide range of output swings are achieved. . The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 shows a diagram illustrating a conventional differential amplifier; Figure 2 shows a diagram that shows a different conventional one. illustrates differential amplifier; Fig. 3 shows a diagram illustrating a differential amplifier according to an exemplary embodiment of the present invention; Fig. 4 shows a diagram illustrating a CMOS amplifier corresponding to the inverters of the differential amplifier of Fig. 3; Fig. 5 shows a diagram illustrating a small signal equivalent diagram model of the CMOS inverter of Fig. 4; FIG. 6A shows a graph illustrating simulation waveforms and with an input sweep range of the differential amplifier of FIG. 1 about 0.4 volts; Fig. 6B shows a graph illustrating simulation waveforms in which an input sweep region of the differential amplifier of Fig. 3 is approximately 0.4 volts; Fig. 7A shows a graph illustrating simulation waveforms in which the input sweep range of the differential amplifier of Fig. 1 is approximately 0.04 volts; Fig. 7B shows a graph illustrating simulation waveforms in which the input sweep range of the differential amplifier of Fig. 3 is approximately 0.04 volts; FIG. 8A shows a graph illustrating simulation waveforms in which the input sweep range of the differential amplifier of FIG. 1 is approximately 0.004 volts; and . . Fig. 8B is a graph showing simulation waveforms. 3 in which the input sweep range of the differential amplifier of FIG. 3 is approximately 0.004 volts.
    Detailed illustrative embodiments of the present invention are described herein. However, specific structural and functional details described herein only serve the purpose of describing exemplary embodiments of the present invention. This invention can be embodied in many other forms and should not be understood as being limited to the embodiments described herein.
    While the invention is susceptible. for various modifications and alternative forms, therefore, specific embodiments thereof have been shown by way of example in the drawings and will be described here in detail. It is to be understood, however, that it is not intended to limit the invention to certain forms described, but rather that the invention encompasses all modifications, equivalents, and alternatives that fall within the spirit and scope of the invention. Like numbers refer to like elements through the description of the figures.
    FIG. -3 shows a circuit illustrating a differential amplifier according to an exemplary embodiment of the present invention.
    As shown in Fig. 3, the differential amplifier according to one embodiment of the present invention comprises a first current source 310, a second current source 320, a first inverter 330, a second inverter 340, and a self-adjusting control circuit 350. The. self-adjustment control circuit 350 includes a third inverter 351 and a fourth inverter 352.
    The first current source 310 comprises a pair of PMOS transistors Mil and M12 that are connected between a first power voltage VDD and a first node N4. The second current source 320 comprises a pair of NMOS transistors M1 and M2 which are connected between a second power voltage Vss and a second node N1.
    The first inverter 330 includes PMOS transistor M7 and NMOS transistor M3. The PMOS transistor M7 and the NMOS transistor M3 are serially connected between the first node N4 and the second node N1. The first inverter 330 amplifies an input signal. which is input via an input terminal IN for generating an inverted output signal which is supplied to an inverted output terminal OUTB. The second inverter 340 includes PMOS transistor M10 and NMOS transistor M6. The PMOS transistor M10 and the NMOS transistor M6 are serially connected between the first node N4 and the second node N. The second inverter 340 amplifies an inverted input signal which is input via an inverted one. input terminal INB for generating an output signal supplied to an output terminal OUT.
    The self-set control circuit 350 is connected between the first node N4 and the second node N1, and. . generates a control signal and an inverted control signal. The control signal and the inverted control signal are provided to the first current source 310 and the second current source 320 via a third node N2 and a fourth node N3.
    The self-set control circuit 350 comprises a third inverter 351 and a fourth inverter.352. The third inverter 351 generates the inverted control signal for controlling the first current source 310 and the second current source 320 via the third node N2. The fourth inverter 352 generates the control signal for controlling the first current source 310 and the second current source 320 via. the fourth node N4 ..
    The third inverter. 351 includes PMOS transistor M8 and NMOS transistor M4. The PMOS transistor M8 and the NMOS transistor M4 are serially connected between the first node N4. and the second node N1. The third inverter 351 amplifies the input signal supplied through the input terminal In for the. generating an inverted control signal. The inverted control signal is supplied to the first current source 310 and the second current source 320 via the third node N2.
    The fourth inverter 352 includes PMOS transistor M9 and NMOS transistor M5. The PMOS transistor M9 and the NMOS transistor M5 are serially connected between the first node N4 and the second node N. The fourth inverter 352 amplifies the inverted input signal supplied via the inverted input terminal INB for generating a control signal. The control signal is supplied to the first current source 310 and the second current source 320 via the fourth node N3. The inverted control signal is supplied to the gate i of the PMOS transistor Mil of the first current source 310 and the gate of the. NMOS transistor M1 of the second current source 320. The control signal is supplied to the gate of the PMOS transistor M12 of the first current source 310 and the gate of the NMOS transistor M2 of the second current source 320.
    The differential amplifier that is illustrated in. FIG. 3 provides a constant bias current without using additional circuits for driving the current sources. The operation of the differential amplifier illustrated in FIG. 3 will be described in detail below.
    When an input voltage (i.e., small signal voltage.) Applied to the input terminal IN increases and another input voltage (ie small signal voltage) applied to the input terminal INB decreases, the current flowing through the PMOS transistor M8 from the third inverter 351 and takes the current flowing through the NMOS transistor M4 from the third inverter. 351, so that the voltage of the third node N2 decreases. . Therefore, the current flowing through the PMOS transistor M1 of the first current source 310 increases, and the current passing through the NMOS transistor M1 of the second current source 320 decreases.
    At the same time, the current that runs through the. PMOS transistor M9 of the fourth inverter 352. and the current flowing through the NMOS transistor M5 from the fourth inverter 352 decreases so that the voltage of the fourth node N3 increases. Therefore, the current flowing through the PMOS transistor M12 from the first current source 310 decreases, and the current flowing through the NMOS transistor M2 from the second current source 320 increases.
    On the other hand, when the input voltage applied to one input terminal INB decreases and the input voltage applied to the other input terminal INB increases, the current flowing through the PMOS transistor M8 of the third inverter 351 increases and the current flowing by the NMOS transistor M4 from the third inverter 351 so that the voltage of the third node N2 increases. Therefore, the current flowing through the PMOS transistor Mil from the first current source 310 decreases and the current flowing through the NMOS transistor M1 from the second current source 320 increases.
    At the same time, the current flowing through the PMOS transistor M9 of the fourth inverter 352 decreases and the current flowing through the NMOS transistor M5 of the fourth inverter 352 increases so that the voltage of the fourth node N3 decreases. Therefore, the current flowing through the PMOS transistor M12 of the first current source 310 increases. and the current flowing through the NMOS transistor M2 from the second current source 320 decreases.
    As a result, the PMOS transistors M1 and M12 of the first current source 310 operate in a complementary manner to each other to provide constant current, and the NMOS transistor M1 and M2 of the second current source 320 operate in a complementary manner to each other for also providing constant current. Moreover, the current through the PMOS transistor Mil increases when the current through the NMOS. transistor M2 increases and the current through the PMOS transistor Mil decreases when the current through the NMOS transistor M2 decreases. The current through the PMOS transistor M12 increases as the current through the NMOS transistor M1 decreases and the current through the PMOS transistor M12 decreases as the current through the NMOS transistor M1 decreases. Therefore, when the input signal and the inverted input signal are complementary small signals, the first bias current provided is kept substantially constant by the first current source 310 and the second bias current provided by the second current source 320. . Therefore, in the amplifier circuit configuration of FIG. 3, there is no mismatch between the first bias current and the second bias current, and the first current source and the second current source operate as. ideal power sources. When complementary small signals are applied to the input terminals. IN and INB, the first current source 310 and the second current source 320 serve as ideal current sources without the need for additional circuits for driving the first current source 310 and the second current source 320.
    The PMOS transistors Mil and M12. of the first current source 310 and the NMOS transistors M1 and M2 of the second current source 320 of FIG. 3 operate in a linear region of the devices. The first node N4 is held as the voltage level of approximately the first power voltage VDD, and the second node N1 is held as the voltage level of approximately the second power voltage Vss. The output signals at the output terminals OUT and OUTB can have a wider voltage signal sweep range. The wide sweep range of the output signals leads to a larger one. noise margin when the differential amplifier cooperates with other logic circuits.
    In the following, the gain of the first inverter 330 and the second inverter 340 of the differential amplifier illustrated in FIG. explained in detail. Both the first inverter 330 and the second inverter 340 have the structure of a CMOS inverter. In the following, the operation and gain of the first inverter 330 is explained as an example.
    FIG. 4 shows a circuit diagram illustrating a CMOS inverter corresponding to the inverters of the differential amplifier of FIG. 3.
    The CMOS inverter of FIG. 4 is identical to the first inverter 330 of FIG. 3 except that a PMOS transistor MP is directly connected to the first power supply voltage VDD and an NMOS. . transistor. MN is directly connected to the second power voltage Vss. Instead are the transistors. of the first inverter of FIG. 3 serially connected between the first node N4 and the second node N1. However, the voltage level of the first node N4 is substantially equal to the first power voltage VDD and the voltage level of the second node N1 is substantially equal to the second power voltage Vss when small signal inputs are applied to the differential. 3. Thus, in the following, the small signal gain of the CMOS inverter of FIG. 4 will be described.
    FIG. 5 shows a circuit diagram that a. small signal equivalent .circuit model of the CMOS. inverter of FIG. 4.
    Referring to FIG. 5, gmp and g ^ represent transconductances of the PMOS transistor MP and. the NMOS transistor MN, and rop and ron are small signal output resistors of. the PMOS transistor MP and the NMOS transistor MN respectively. In Fig. 5, vi and vo are the small signal components of the input voltage Vi and the output voltage Vo, respectively. Referring to Fig. 5, the small signal gain of the CMOS inverter illustrated in Fig. 4 can be calculated as shown in expression 2. <Expression 2>
    The small signal gain of the first inverter 330 illustrated in FIG. 3 is calculated as shown in expression 2, and the small signal gain of the second inverter 340 is identical to the gain of the first inverter 330 since the structure of the first inverter 330 is identical to that of the second inverter 340. The differential amplifier illustrated in FIG. 3 therefore has almost the same gain as the gain described in expression 2.
    The differential amplifier of FIG. 3 has a gain that is approximately twice that of the differential amplifier of FIG. 1-
    FIG. 6A is a graph illustrating simulation waveforms of input / output signals in which the input sweep range of the differential amplifier of FIG. 1 is approximately 0.4 volts.
    The. simulation waveform of FIG. 6A is a simulation result when the first power voltage VDD is approximately 1.8 volts, the second power voltage Vss is approximately 0 volts, the frequency of the input signals is approximately 200 MHz, and the input signals have a sweep range between approximately 0.7 volts and about 1.1 volts. In other words, the input signals swing with a width of about 0.2 volts relative to about 0.9 volts. In the following, the input signals are shown as V (IN.INB) = 0.2 volts. A signal V (OÜT) represents the output signal of the output terminal OUT illustrated in FIG. A signal V (OUTB) represents the output signal from the output terminal OUTB illustrated in FIG. As shown in FIG. 1 and: FIG. 6A, the sweep range of the signal V (OUT) is limited by the current source Iss and the transistor M2 or the current source Iss and the transistor M1. The sweep range of the signal V (OUTB) is narrower than that of the signal V (OUT) through the diode-connected transistor M3. In Fig. 6A, the signal V (OUT) swings in a range of about 0.46 volts to about 1.59 volts, and AV (OUT) is about 1.13 volts.
    FIG. 6B shows a graph illustrating simulation waveforms of input / output signals where the input sweep range of the differential amplifier of FIG. 3 is approximately 0.4 volts. The simulation waveform illustrated in Fig. 6B is a simulation result when the first power voltage VDD is about 1.8 volts, the second power voltage Vss is about 0 volts, the frequency of the input signals V (IN.INB) about 200 MHz and the input signal V (IN.INB) swings with a swing width of about 0.2 volts relative to about 0.9 volts. A signal V (OUT) represents it. output signal from the output terminal OUT of FIG. 3. A signal V (OUTB) represents the output signal from the output terminal OUTB of FIG. 3. As shown in FIG. 3 and FIG. 6B, the transistors M1, M2, Mil and M12 of the first current source 310 and the second current source 320 of Fig. 3 in a linear region so that the first node N4 and the second node N1 are held respectively if the voltage is approximately equal to the first power voltage VDD and the voltage is approximately equal to the second power voltage Vss . The output signals V (OUT) and V (OUTB) therefore have full swing level and show symmetry with respect to each other. The AV (OUT) output area is approximately 1.41 volts.
    In comparison with Fig. 6B with Fig. 6A, the differential amplifier of Fig. 3 has a greater gain, symmetrical output signals from the output terminals OUT and OUTB and a wider sweep range than the differential amplifier of Fig. 1. Moreover, the bias voltage of the output signal is closer to the bias voltage, ie about 0.9 volts, of the input signal of the differential amplifier of Figure 3, compared to the bias voltage of the differential amplifier of Figure 1.
    FIG. 7A shows a graph illustrating simulation waveforms of input / output signals in which the input sweep range of the differential amplifier of FIG. 1 is approximately 0.04 volts. As shown in Fig. 7A, the output region AV (OUT) is approximately 0.15 volts.
    FIG. 7B shows a graph illustrating simulation waveforms of input / output signals in which the input sweep range of the differential amplifier of FIG. 3 is approximately 0.04 volts. As shown in Fig. 7B, the output region AV (OUT) is approximately 0.18 volts.
    FIG. 8A shows a graph illustrating simulation waveforms of input / output signals in which the input sweep region of the differential amplifier of FIG. 1 is approximately 0.004 volts. As shown in Fig. 8A, the output region AV (OUT) is approximately 14 millivolts.
    FIG. 8B shows a graph illustrating simulation waveforms of input / output signals in which the input sweep region of the differential amplifier of FIG. 3 is approximately 0.004 volts. As shown in Fig. 8B, the output region AV (OUT) is approximately 21 millivolts.
    In conclusion, the simulation results of Figs. 6A to Fig. 8B show that the differential amplifier of Fig. 3 according to the exemplary embodiment of the present invention has a greater gain and wider output sweep range than the conventional differential amplifier of Fig. 1. In particular referring to the simulation results of Figs. 8A and Fig. 8B, the differential amplifier according to the exemplary embodiment of the present invention has a gain about twice as high as that of the conventional amplifier when the input signals have a small sweep range such as about 0.04 volts. The differential amplifier according to the exemplary embodiment of the present invention provides a substantially constant bias current without the need for additional circuitry for driving current sources when complementary small signals are supplied thereto. The differential amplifier according to the exemplary embodiment of the present invention adopts the structure of CMOS inverter to achieve a high small signal gain.
    The transistors of the first current source and the second current source operate in the linear region so that the differential amplifier according to the exemplary embodiment of the present invention achieves a wide range of output sweep and a high noise margin.
    The differential amplifier according to the pre-image embodiment of the present invention furthermore has an up / down and left / right symmetrical structure for achieving, a fully differential output and to provide reduced distortion.
    As mentioned above, the differential amplifier according to the exemplary embodiment of the present invention does not require additional circuits for driving current sources or voltage sources. In this way power consumption and size of the circuit are reduced.
    Although exemplary embodiments of the present invention and the advantages thereof have been described in detail, it is to be understood that various changes, substitutions, and modifications may be made without departing from the spirit of the invention.
    权利要求:
    Claims (11)
    [1]
    CONCLUSIONS 1. Differential amplifier comprising: a first current source that is connected between a first. a power voltage and a first node, which is adapted to provide a first bias current in response to a control signal and an inverted control signal; ; a second current source which is connected between a second power voltage and a second node and which is arranged for the. providing a second bias current in response to the control signal and the inverted control signal; 1; a first inverter which is connected between the first node and the second node and which is adapted to amplify an input signal for. generating an inverted output signal; a second inverter connected between the first; node, and the second node, and which is adapted to amplify an inverted input signal to generate an output signal; and a self-setting control circuit that is connected between the first node and the second node and which is adapted to generate the control signal and the inverted control signal for controlling the first bias current and the second bias current in response to the input signal and the inverted input signal.
    [2]
    ,. 2. Differential amplifier according to claim. 1, wherein the self-adjustment control circuit comprises: a: third, inverter adapted to amplify the input signal for generating the inverted control signal; and a. fourth inverter that. is adapted to amplify the inverted input signal for generating the control signal.
    [3]
    The differential amplifier according to claim 2, wherein the first, second, third and fourth inverters are CMOS inverters in which a first PMOS transistor and. a first NMOS transistor are serially bonded to each other.
    [4]
    4: A differential amplifier according to any one of the preceding claims, wherein the first current source comprises: a first undercurrent source that is connected between the first power voltage and the first node and which is arranged to provide a first under bias current to the first node in response to the inverted control signal; and a second undercurrent source that is connected between the first power voltage and the first node and which is arranged to provide a second undercurrent current. the first node in response to the control signal, wherein the second sub-bias current is complementarily controlled relative to the first sub-bias current, and wherein the first current source adds the first sub-bias current and the second sub-bias current to generate the first bias current .
    [5]
    The differential amplifier of claim 4, wherein the second current source comprises: a. first undercurrent drain connected between the second power voltage and the second node and adapted to provide a third undercurrent current to the second node in response to the inverted control signal; and a second undercurrent drain connected between the second power voltage and the second node. which is arranged to provide a fourth sub-bias current to the second. node in response to the control signal, wherein the fourth sub-bias current is complementarily controlled with respect to the third sub-bias current, and wherein the second current source adds the third sub-bias current and the fourth sub-bias current to generate the second bias current. . .
    [6]
    6. Differential amplifier according to ·. claim 5, wherein the first sub-bias current increases as the fourth sub-bias current increases, the. first sub-bias current decreases as the fourth sub-bias current decreases, the second sub-bias current increases as the third sub-bias current increases and the second sub-bias current decreases as the third sub-bias current decreases.
    [7]
    The differential amplifier according to claim 6, wherein a magnitude of the first bias current is the same as that of the second bias current.
    [8]
    A differential amplifier according to any of claims 5-7, wherein the first undercurrent source and the second undercurrent source comprise second PMOS transistors, respectively, and the first undercurrent drain and the second undercurrent drain and second NMOS transistors, respectively.
    [9]
    The differential amplifier according to claim 8, wherein the second PMOS transistors and the second NMOS transistors operate in a linear region.
    [10]
    The differential amplifier according to any of the preceding claims, wherein the first power voltage is approximately 1.8 volts and the second power voltage is approximately 0 volts. .
    [11]
    A differential amplifier according to any one of the preceding claims, wherein the input signal and the inverted input signal comprise small signals set to approximately 0.9 volts.
    类似技术:
    公开号 | 公开日 | 专利标题
    NL1029337A1|2006-01-10|Self-adjusted differential amplifier.
    US7391825B2|2008-06-24|Comparator circuit having reduced pulse width distortion
    US7884671B2|2011-02-08|Low power operational amplifier
    US6433637B1|2002-08-13|Single cell rail-to-rail input/output operational amplifier
    US7138866B2|2006-11-21|Operational amplifier including low DC gain wideband circuit and high DC gain narrowband gain circuit
    JP2004032689A|2004-01-29|Current-sense amplifier
    US6937100B2|2005-08-30|Amplifier circuit with common mode feedback
    EP1895656A2|2008-03-05|High gain, high speed comparator operable at low current
    US6762646B1|2004-07-13|Modified folded cascode amplifier
    US7091754B2|2006-08-15|CMOS LvPECL driver with output level control
    US6831501B1|2004-12-14|Common-mode controlled differential gain boosting
    US7030696B2|2006-04-18|Differential amplifier and semiconductor device
    US8130034B2|2012-03-06|Rail-to-rail amplifier
    US20070024367A1|2007-02-01|Operational amplifier and constant-current generation circuit using the same
    US7071772B2|2006-07-04|Differential amplifier
    US8081015B2|2011-12-20|Differential amplifier with a feedback unit
    JP2005328151A|2005-11-24|Amplifier circuit
    JP2001339259A|2001-12-07|Differential amplifier circuit and semiconductor integrated circuit device
    KR100453424B1|2004-10-15|Semiconductor integrated circuit
    US6791412B2|2004-09-14|Differential amplifier output stage
    US6710660B1|2004-03-23|Class B power buffer with rail to rail output swing and small deadband
    US6930542B1|2005-08-16|Differential gain boosting
    KR100668455B1|2007-01-16|Variable gain amplifier
    US8878609B2|2014-11-04|Differential amplifier circuit
    JP4867066B2|2012-02-01|Amplifier circuit
    同族专利:
    公开号 | 公开日
    KR20060004260A|2006-01-12|
    US20060012429A1|2006-01-19|
    CN1719722A|2006-01-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US4965825A|1981-11-03|1990-10-23|The Personalized Mass Media Corporation|Signal processing apparatus and methods|
    US5808608A|1990-09-10|1998-09-15|Starsight Telecast, Inc.|Background television schedule system|
    US5861881A|1991-11-25|1999-01-19|Actv, Inc.|Interactive computer system for providing an interactive presentation with personalized video, audio and graphics responses for multiple viewers|
    US5357276A|1992-12-01|1994-10-18|Scientific-Atlanta, Inc.|Method of providing video on demand with VCR like functions|
    US5440334A|1993-02-01|1995-08-08|Explore Technology, Inc.|Broadcast video burst transmission cyclic distribution apparatus and method|
    DE69319327T2|1993-05-19|1998-10-29|Alsthom Cge Alcatel|Video server|
    DE69517647T2|1994-04-25|2001-02-22|Sony Corp|VIDEO SIGNAL PLAYER|
    JPH0879685A|1994-08-31|1996-03-22|Sony Corp|Program reproducing device for near-video-on-demand system|
    JP3864422B2|1994-09-16|2006-12-27|ソニー株式会社|Data transmission apparatus and data transmission method|
    US5614940A|1994-10-21|1997-03-25|Intel Corporation|Method and apparatus for providing broadcast information with indexing|
    US5682597A|1995-06-15|1997-10-28|International Business Machines Corporation|Hybrid video-on-demand based on a near-video-on-demand system|
    US5778187A|1996-05-09|1998-07-07|Netcast Communications Corp.|Multicasting method and apparatus|
    US5953276A|1997-12-18|1999-09-14|Micron Technology, Inc.|Fully-differential amplifier|
    US6920187B2|2002-10-02|2005-07-19|Micron Technology, Inc.|Constant delay zero standby differential logic receiver and method|
    US6924668B2|2003-09-25|2005-08-02|Infineon Technologies Ag|Differential to single-ended logic converter|DE102006020485B4|2006-04-28|2019-07-04|Atmel Corp.|operational amplifiers|
    JP4653046B2|2006-09-08|2011-03-16|株式会社リコー|Differential amplifier circuit, voltage regulator using the differential amplifier circuit, and differential amplifier circuit operation control method|
    US7554405B2|2007-05-02|2009-06-30|Samsung Electronics Co., Ltd.|Adaptive biasing input stage and amplifiers including the same|
    US9077289B2|2013-06-14|2015-07-07|Qualcomm Incorporated|Self-biased receiver|
    KR102166913B1|2014-01-03|2020-10-16|삼성전자주식회사|Self bias buffer circuit and memory device including the same|
    CN105375890A|2014-08-20|2016-03-02|中芯国际集成电路制造有限公司|Low-noise amplifier|
    CN104753482A|2015-04-06|2015-07-01|王文平|Series feedback balance high-fidelity audio amplifying circuit|
    CN105116954B|2015-09-07|2017-09-01|卓捷创芯科技（深圳）有限公司|A kind of wide input voltage range and the automatic biasing band-gap reference circuit of high accuracy output|
    法律状态:
    2006-03-01| AD1A| A request for search or an international type search has been filed|
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020040053310A|KR20060004260A|2004-07-09|2004-07-09|Self biased differential amplifier|
    [返回顶部]